Mainstream processor chips, both in high performance and low power segments, are increasingly integrating additional functionality such as graphics, display engines, security engines, PCIe™ ports (i.e., ports in accordance with the Peripheral Component Interconnect Express (PCI Express™ (PCIe™)) Specification Base Specification version 2.0 (published 2007) (hereafter the PCIe™ specification) and other PCIe™ based peripheral devices, while maintaining legacy support for devices compliant with a PCI specification such as the Peripheral Component Interconnect (PCI) Local Bus Specification, version 3.0 (published 2002) (hereafter the PCI specification).
Such designs are highly segmented due to varying requirements from the server, desktop, mobile, embedded, ultra-mobile and mobile Internet device segments. Different markets seek to use single chip system-on-chip (SoC) solutions that combine at least some of processor cores, memory controllers, input/output controllers and other segment specific acceleration elements onto a single chip. However, designs that accumulate these features are slow to emerge due to the difficulty of integrating different intellectual property (IP) blocks on a single die. This is especially so, as IP blocks can have various requirements and design uniqueness, and can require many specialized wires, communication protocols and so forth to enable their incorporation into an SoC. As a result, each SoC or other advanced semiconductor device that is developed requires a great amount of design complexity and customization to incorporate different IP blocks into a single device.
One such area of design interest is arbitration. To prevent deadlocks and stalls in a system, an arbiter may be present to receive requests from multiple agents and arbitrate the requests to provide access grants to resources of the system. In some systems, arbitration is performed according to a fixed priority privilege in which a certain number of grants are allowed to avoid a higher priority requestor from starving lower priority requestors. Grant operation typically starts from the highest priority requestor and proceeds to the lowest priority requestor. In some systems, the lower priority requestor can only receive a grant when higher priority requestors have no active requests or have exhausted their grant count. Requestors commonly receive reloaded grant counts when no active requests are present, every requestor participating in arbitration has exhausted their grant counts, or no active request from any requestor with a valid grant count exists.
In a conventional fixed priority arbitration scheme, bandwidth allocation may not be able to be maintained for non-pipelined requests. These requests are received in the arbiter from a requestor that cannot, for some reason, maintain back-to-back requests. As a result, in a platform having pipelined and non-pipelined input/output (I/O) requestors, non-pipelined requestors can realize significant bandwidth degradation.